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System Workbench for STM32


ARM Cortex M4 SVC interrupt causes usage fault

I'm trying to write a context switch assembly on STM32F411E but I encounter a usageFault right after I make a second call to the SVC 0 (in my second task) instruction.

Here are some of the status register values after I make a call to SVC 0, in my second task:

CCR = 0x00000218
HFSR = 0x40000000
CFSR = 0x00000000
DFSR = 0x0000000b
BFAR = 0xe000ed38
AFSR = 0x00000000
MMFSR = 0x00000000
MMFAR = 0xe000ed34

Looks like DFSR might provide the biggest clue but I am still not sure what is causing this fault. Has anyone encountered a similar error and can anyone assist me with finding the source of this fault? Why would first call to SVC 0 (in task1) work but the second call to SVC 0 (in task2) fail?

Here's my context switch code:

***************************************************
* initActivate
*
* Description: context switch routine for tasks
*
* Input:
*
* Output:
*
* Return:
*
* Note:
*
*
***************************************************/
activate:

cpsie i

mrs ip, psr
push {r4, r5, r6, r7, r8, r9, r10, r11, ip, lr}

ldmfd r0!, {r4, r5, r6, r7, r8, r9, r10, r11, ip, lr}

msr control, ip
isb
msr psp, r0

/* jump to user task*/
bx lr


/***************************************************
* SVC_Handler
*
* Description:
*
* Input:
*
* Output:
*
* Return:
*
* Note: supervisor call (handler mode)
*
*
***************************************************/
.thumb_func
SVC_Handler:

mrs r0, psp
stmdb r0!, {r4, r5, r6, r7, r8, r9, r10, r11, ip, lr}

/* load kernel state */
pop {r4, r5, r6, r7, r8, r9, r10, r11, ip, lr}
msr psr_nzcvq, ip

/* back to the thread mode if no other active exception */
bx lr