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System Workbench for STM32


Problem encountered while flashing code to stm32f103c8t6 using st-link v2

India

Hi, Please help me someone to overcome this problem.
In console I am getting this message

'

Open On-Chip Debugger 0.10.0-dev-00270-g7ec9836 (2016-05-18-14:26)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 1000 kHz
adapter_nsrst_delay: 100
srst_only separate srst_nogate srst_open_drain connect_assert_srst
srst_only separate srst_nogate srst_open_drain connect_assert_srst
Info : Unable to match requested speed 1000 kHz, using 950 kHz
Info : Unable to match requested speed 1000 kHz, using 950 kHz
Info : clock speed 950 kHz
Info : STLINK v2 JTAG v17 API v2 SWIM v4 VID 0x0483 PID 0x3748
Info : using stlink api v2
Info : Target voltage: 3.245003
Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
Error: timed out while waiting for target halted
TARGET: stm32f1x.cpu - Not halted
in procedure 'program'
in procedure 'reset' called at file "embedded:startup.tcl", line 478
in procedure 'ocd_bouncer'

    • Unable to reset target **

shutdown command invoked


''

hi, i met the same problem ,and after read this page, i had solved .


------------------------------
seems the simplest way to deal with this is to just use

reset_config none separate

Then the reset is done internally over the SWD channel with no pins used.

--------------------------
edit the *.cfg file in the project as below:

# use hardware reset, connect under reset
#reset_config srst_only srst_nogate
reset_config none separate

India

__edit the *.cfg file in the project as below:

  1. use hardware reset, connect under reset
  2. reset_config srst_only srst_nogate

reset_config none separate__


I edited the .cfg file as you mentioned, now problem is solved.

Thank you!